1 of 6 111799 features all-silicon timing circuit three independent buffered delays initial delay tolerance 1.5 ns stable and precise over temperature and voltage leading and trailing edge precision preserves the input symmetry standard 8-pin dip, 8-pin soic vapor phasing, ir and wave solderable available in tape and reel pin assignment pin description in1-in3 - input signals out1-out3 - output signals nc - no connection v cc - supply voltage gnd - ground (sub) - internal substrate connection, do not make any external connections to these pins description the ds1033 series is a low-power +3.3 volt version of the ds1035. it is characterized for operation over the range of 2.7v to 3.6v. the ds1033 series of delay lines have three independent logic buffered delays in a single package. it is available in a standard 8-pin dip, 150-mil 8-pin mini-soic. the device features precise leading and trailing edge accuracies. it has the inherent reliability of an all- silicon delay line solution. the ds1033?s nominal tolerance is 1.5 ns and an additional tolerance over temperature and voltage of 1.0 ns for the faster delays. detailed specifications are shown in table 1. standard delay values are indicated in table 1. customers may contact dallas semiconductor at (972) 371-4348 for further information. ds1033 3-in-1 low voltage silicon delay line www.dalsemi.com ds1033z 8-pin soic (150-mil) see mech. drawings section in1 in2 in3 gnd v cc out3 out1 out2 1 2 3 4 8 7 6 5 ds1033m 8-pin dip see mech. drawings section v cc out3 out1 out2 in1 in2 in3 gnd 1 2 3 4 8 7 6 5
ds1033 2 of 6 logic diagram figure 1 part number delay table (t plh , t phl ) table 1 tolerance over temperature and voltage (note 2) part number delay per output (ns) (note 1) initial tolerance (note 1) v cc =3.3v = == = 0.3v v cc =2.7v ds1033-8 0 8/8/8 1.5 ns 1.0 ns 1.5 ns ds1033-10 10/10/10 1.5 ns 1.0 ns 1.5 ns ds1033-12 12/12/12 1.5 ns 1.0 ns 1.5 ns ds1033-15 15/15/15 1.5 ns 1.5 ns 2.0 ns ds1033-20 20/20/20 1.5 ns 1.5 ns 2.5 ns ds1033-25 25/25/25 2.0 ns 2.0 ns 3.5 ns ds1033-30 30/30/30 2.0 ns 2.0 ns 5.0 ns notes: 1. nominal conditions are +25 c and v cc =+3.3 volts. 2. temperature range of 0 c to 70 c. 3. delay accuracy is for both leading and trailing edges.
ds1033 3 of 6 test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters of the ds1033. the input waveform is produced by a precision pulse generator under software control. time delays are measured by a time interval counter (20 ps resolution ) connected to the output. the ds1033 output taps are selected and connected to the interval counter by a vhf switch control unit. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus. ds1033 test circuit figure 2
ds1033 4 of 6 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +6.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a =0c to 70c) parameter symbol test condition min typ max units supply voltage v cc 2.7 3.3 3.6 v active current i cc v cc =3.6v period=1 s 25 ma high level input voltage v ih 2.0 v cc +0.5 v low level input voltage v il -0.5 0.8 v input leakage i l 0v v i v cc -1.0 1.0 a high level output current i oh v cc =2.7v v oh =2v -1.0 ma low level output current i ol v cc =2.7v v ol =0.4v 8ma ac electrical characteristics (t a =+25c) parameter symbol min typ max units notes period t period 2 (t wi )ns2 input pulse width t wi 100% of tap delay ns 2 input-to-tap output delay t plh, t phl table 1 ns output rise or fall time t or, t of 2.0 3.0 2.5 3.5 ns ns 3 4 power-up time t pu 100 ms capacitance (t a =+25c) parameter symbol min typ max units notes input capacitance c in 10 pf
ds1033 5 of 6 test conditions ambient temperature: 25 c = 3 c supply voltage (v cc ): 3.3v = 0.1v input pulse: high: 3.0v = 0.1v low: 0.0v = 0.1v source impedance: 50 ? = max. rise and fall time: 3.0 ns max. - measured between 0.6v and 2.4v. pulse width: 500 ns pulse period: 1 s output load capacitance: 15 pf output: each output is loaded with the equivalent of one 74f04 input gate. data is measured at the 1.5v level on the rising and falling edges. note: the above conditions are for test only and do not restrict the devices under other data sheet conditions. timing diagram notes: 1. all voltages are referenced to ground. 2. pulse width and duty cycle specifications may be exceeded; however, accuracy will be application- sensitive with respect to de-coupling, layout, etc. 3. v cc =3.3v = 10%. 4. v cc =2.7v.
ds1033 6 of 6 terminology period : the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5 volt point on the leading edge and the 1.5 volt point on the trailing edge, or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall ( input fall time): the elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. t plh (time delay, rising): the elapsed time between the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse.
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1033 part number table notes: see the ds1033 quickview data sheet for further information on this product family or download the ds1033 full data sheet (pdf, 51kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1033m-12 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1033m-10 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1033m-8 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-2 * 0c to +70c rohs/lead-free: no materials analysis
ds1033m-25 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1033m-20 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-20/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-10/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-25/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-12 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-25 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-12/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-30 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033c-902/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033c-902 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis
ds1033c-803/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033c-803 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-8+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * 0c to +70c rohs/lead-free: yes materials analysis ds1033z-20 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-15 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis ds1033z-8 8ns soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * 0c to +70c rohs/lead-free: no materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy
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